1. Field
Embodiments relate to processors, methods performed by processors, systems incorporating processors, or instructions processed by processors. In particular, embodiments relate to processors, methods, systems, or instructions to unpack packed data in multiple lanes.
2. Background Information
Improving the performance of computers and other processing systems generally tends to increase the amount of data that may be processed and/or provide a better user experience. As computer and other processing systems handle increasingly larger amounts of data, techniques to expedite such processing of data tend to become more important.
Single Instruction, Multiple Data (SIMD) architectures are one way to expedite processing of data. In SIMD architectures, instead of one instruction operating on only one data element, the instruction may operate on multiple data elements simultaneously or in parallel. Representatively, in SIMD architectures multiple data elements may be packed within one register or memory location. Parallel execution hardware responsive to the instruction may perform multiple operations simultaneously or in parallel. Such SIMD architectures tend to significantly improve system performance.
One known type of SIMD instruction is an unpack instruction. Some known processors include a variety of different unpack instructions. For example, the Intel® Core™ 2 Duo Processor, among others from Intel Corporation, includes various unpack instructions such as those detailed in the Intel Architecture Software Developer's Manual: Vol. 2: Instruction Set Reference, 1999 (Order Number 243191).
However, additional unpack instructions and operations may be useful under some conditions and for some applications.